Multi-layer interconnect lines are commonly used in the semiconductor industry. Metallization lines are connected via studs, commonly made of tungsten (W). The lines themselves are often made of aluminum (Al) and/or copper (Cu). Two problems that are commonly encountered with such multi-layer interconnect line structures are electromigration and metal creep. Both of these phenomenon involve the transport of metal atoms along the direction of electron flow in the lines, and can lead to failure of the lines.
Al-Cu electromigration in a structure with Al-Cu lines and W studs is now well established. The phenomenon occurs because Cu diffusivity through W is much lower than through Al. Therefore the Cu is depleted from the area of the W stud by the current flow and not replaced, leading to failure at the W to Al-Cu stud interface.
Metal creep, on the other hand, occurs due to the differences in the thermal coefficients of expansion between metals, insulators, and silicon wafers. The differences in thermal coefficients of expansion can build up stress in the metal lines, which can lead to migration of atoms in the line to the various areas of high stress and strain. This migration of atoms forms voids or vacancies in the metal line which can cause creep failure.
Another phenomenon that is frequently observed is that short lines, i.e. less than about 50 microns, do not fail due to electromigration. The explanation for this is that the flow of Cu and Al out of the stud region is counterbalanced by other forces (either stress or concentration gradients) which cause a migration of material in the opposite direction. A steady state with no net material transport is achieved and there is no stud interconnect failure by electromigration. Current technologies for providing such short lines involve running along a line on one level for 50 microns, then dropping through a stud to another level to run 50 microns, and then moving back up through a stud to another level, etc. This is not a very practical solution to electromigration problems, however, due to the amount of space taken up by the multi-level interconnect line structure.
An attempt to overcome electromigration problems is shown in Cronin, J. E., et al., "Elimination of CMOS Electromigration-Induced Extrusions", IBM Tech Discl. Bull. Vol. 31, No. 6 (November 1988), pp. 461-462. Cronin et al. show a wiring structure in which tungsten links are interposed in multi-level aluminum-copper lines to increase electromigration resistance. However, the links are not in the same plane as the metal lines, thus not providing a practical solution to electromigration due to the space required. Furthermore, the links are spaced 300 microns apart which does not optimize electromigration reduction.
Attempts have also been made to overcome electromigration problems by providing longitudinal barrier layers in lines. Cook, H. C., et al., "Process and Structure for Improved Electromigration Resistance", IBM Tech. Discl. Bull. Vol. 31, No. 10B (March 1990), pp. 112-113, disclose an aluminum-copper line formed in a titanium-tungsten trough to provide a low resistivity line with improved electromigration resistance. Tungsten stud interconnections are provided above and below the lines. In this arrangement, the refractory metals serve as longitudinal shunts that can still carry electric current even after substantial aluminum migration.
Another reference disclosing the formation of longitudinal diffusion barriers in aluminum lines is Howard, J. K., et al., "Fabrication of Intermetallic Diffusion Barriers for Electromigration in Narrow-Line Stripes", IBM Tech. Discl. Bull. Vol. 20, No. 9 (February 1978), pp. 3477-3479. Howard et al. disclose the formation of regions of intermetallic compounds of aluminum/transition metal to increase electromigration resistance in aluminum lines.
Additional solutions to the problem of electromigration in lines are always desirable, which can control electromigration and metal creep problems while minimizing the space utilized by the line structure.